Paper Info
Title
On-Chip Instruction Generation for Cross-Layer CNN Accelerator on FPGA
Abstract
Convolutional neural networks (CNN) are gaining popularity in the field of computer vision. CNN-based methods are computational-intensive and resource-consuming, thus are hard to be integrated into embedded systems and applied to real-time task scenarios. Many FPGA based CNN accelerators have been proposed to get higher performance. Cross-layer CNN accelerator is designed to reduce the data transfer by fusing several layers. However, the instruction size that needs to be transferred is usually considerable, leading to a performance drop of cross-layer accelerators. In this study, we develop an on-chip instruction generation method based on the cross-layer accelerator to reduce the total instruction size transferred to the chip. We design the corresponding hardware module and modify existing object detection models according to the hardware structure to improve the accuracy of object detection tasks. The evaluation results show that in the same calculation process, our accelerator can achieve 35% data transfer reduction on the VGG16 network. The average instruction size and compilation time are reduced by 95% using our instruction generation method. The performance of the accelerator reaches 1414 GOP/s.
Year
DOI
Venue
2019
10.1109/ISVLSI.2019.00011
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Keywords
Field
DocType
FPGA,CNN,ISA,Cross-Layer,Object Detection
Object detection,System on a chip,Data transmission,Task analysis,Instruction set,Convolutional neural network,Computer science,Field-programmable gate array,Chip,Computer hardware
Conference
ISSN
ISBN
Citations 
2159-3469
978-1-7281-3392-8
0
PageRank 
References 
Authors
0.34
7
5
Name
Order
Citations
PageRank
Yiming Hu163944.91
Shuang Liang26012.33
Jincheng Yu331519.49
Yu Wang42279211.60
Huazhong Yang52239214.90