Name
Title | ||
|---|---|---|
Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone |
Abstract | ||
|---|---|---|
Thanks to their intrinsic pipelining and their globally-asynchronous locally-synchronous nature, quasi-delay-insensitive asynchronous networks on chip can provide high throughput and low latency especially suited to chip-level interconnect. We present the substitution of the multi-clock-domain NoC of a Qualcomm mobile platform by an equivalent ANoC robust asynchronous NoC, relying on the existing network interfaces and automated tools, with a hierarchical substitution of the NoC backbone. Given a raw data-rate twice-higher than the synchronous NoC allowing in-network serialization by two, we show that this integration of an asynchronous NoC can improve system latency or area by 24% with no degradation of throughput and minimal impact on peak power consumption. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ASYNC.2019.00014 | 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) |
Keywords | Field | DocType |
Asynchronous Network on Chip,GALS design,System Level Interconnect,Network on Chip | Asynchronous communication,Pipeline (computing),Serialization,Latency (engineering),Computer science,Network on a chip,Throughput,Latency (engineering),Embedded system,Network interface | Conference |
ISSN | ISBN | Citations |
2643-1394 | 978-1-5386-4748-6 | 0 |
PageRank | References | Authors |
0.34 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yvain Thonnart | 1 | 349 | 32.39 |
| Pascal Vivet | 2 | 606 | 53.09 |
| Shikhanshu Agarwal | 3 | 0 | 0.68 |
| Ramesh Chauhan | 4 | 0 | 0.34 |