Title
A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols
Abstract
Many integrated circuits now consist of multiple processing elements that can be regularly tiled across the two-dimensional surface of a die. A regular grid-based network-on-chip shares resources that simplify communication between components at the cost of increased latency, particularly under congestion. This work reports on several approaches to improve the quality of asynchronous network-on-chip design, applied to arrayed communication networks. First, we investigate the effect of replacing long "wrap" lines of a torus with transmission lines and the advantages that this method contributes to such designs. A method of deadlock free routing on torus networks using virtual channels is proven and implemented in a 65nm technology process. Finally, we evaluate the merits of these designs using a highly accurate Verilog simulation model to generate performance and power results.
Year
DOI
Venue
2019
10.1109/ASYNC.2019.00013
2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Keywords
Field
DocType
Network On-Chip,Deadlock,Transmission Line,Asynchronous
Asynchronous communication,Telecommunications network,Handshake,Computer science,Deadlock,Network on a chip,Electric power transmission,Verilog,Computer hardware,Integrated circuit
Conference
ISSN
ISBN
Citations 
2643-1394
978-1-5386-4748-6
0
PageRank 
References 
Authors
0.34
15
5
Name
Order
Citations
PageRank
Mackenzie J. Wibbels100.34
Shomit Das200.34
Dheeraj Singh Takur300.34
Venkata Nori400.34
Kenneth S. Stevens518525.65