Name
Abstract | ||
|---|---|---|
Modern semiconductor products adopting worldwide distributed manufacturing face the threat of malicious manipulation. An efficient and correct proof of absence of any modification is targeted to be achieved through the comparison of original layout design data with the physical chip layout recovered by reverse engineering. This paper presents an algorithm for this task. It is validated on design and layout data from sample analysis results on 40 nm layers. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/IVSW.2019.8854432 | 2019 IEEE 4th International Verification and Security Workshop (IVSW) |
Keywords | Field | DocType |
reverse engineering,layout extraction,GDSII,verification,geometric design database system | Page layout,Computer science,Reverse engineering,Distributed manufacturing,Chip,Computer hardware,Layout extraction | Conference |
ISBN | Citations | PageRank |
978-1-7281-2672-2 | 0 | 0.34 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aayush Singla | 1 | 0 | 0.34 |
| Bernhard Lippmann | 2 | 0 | 0.34 |
| Helmut E. Graeb | 3 | 269 | 36.22 |