Name
Abstract | ||
|---|---|---|
In order to solve the problems of delay and crosstalk in RRAM read process, a sense amplifier (SA) circuits with adjustable margin for RRAM read access is designed. The circuit includes delay circuit, sense preamplifier circuit, and read circuit. Based on the characteristics of differential signal on bitline of RRAM during read access, a carefully controlled timing sequence is designed in the new Sense Amplifier (SA) circuit. With the help of a 4-1 delay circuit, the SA can adjust the pre-amplification of differential voltage between bitlines and improve the reliability of read access. The simulation results show that the scheme can successfully identify the high resistance state and low resistance state of the memory cell and output “0” or “1”, solving the problems of delay and crosstalk in read process. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ICICDT.2019.8790865 | 2019 International Conference on IC Design and Technology (ICICDT) |
Keywords | Field | DocType |
RRAM,delay,sense amplifier,read process | Sense amplifier,Preamplifier,Electronic engineering,Resistor,Non-volatile memory,Engineering,Electronic circuit,Resistive random-access memory,Amplifier,Memory cell | Conference |
ISSN | ISBN | Citations |
2381-3555 | 978-1-7281-1854-3 | 0 |
PageRank | References | Authors |
0.34 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jinchen Liu | 1 | 0 | 0.34 |
| Ziou Wang | 2 | 0 | 0.34 |
| Yiping Zhang | 3 | 2 | 1.09 |
| Lijun Zhang | 4 | 245 | 37.10 |