Paper Info
Title
Toward Reliable Extraction of the Properties of Border Traps in Lateral GaN Power MOSFET with a Distributed Network Model
Abstract
Robust gate dielectric and dielectric/semiconductor are highly desired for GaN power MOS devices, while the trapping effect of the border traps close to the MOS interface could lead to reliability issues in those devices. In this paper, a complete model for border traps in lateral GaN MOS diode is proposed based on a distributed network of the border traps and channel resistance. We show that excluding the effect of channel resistance is critical for accurate calculating the distribution of border traps in lateral devices with low channel mobility, such as GaN and SiC MOS devices. The proposed model agrees well with the measured frequency dependent capacitance and conductance curves of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /GaN MOS diode in a gate recessed normally-off GaN power MOSFET. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures.
Year
DOI
Venue
2019
10.1109/ICICDT.2019.8790921
2019 International Conference on IC Design and Technology (ICICDT)
Keywords
Field
DocType
Power Lateral MOSFET,impedance measurement,border traps,channel resistance
Gallium nitride,Capacitance,Semiconductor device modeling,Power MOSFET,Diode,Gate dielectric,Electronic engineering,Engineering,MOSFET,Optoelectronics,Semiconductor
Conference
ISSN
ISBN
Citations 
2381-3555
978-1-7281-1854-3
0
PageRank 
References 
Authors
0.34
0
7
Name
Order
Citations
PageRank
Ruiyuan Yin100.68
Yue Li2610.29
Wei Lin300.34
Cheng P. Wen401.01
Yilong Hao5124.49
Yunyi Fu600.34
Maojun Wang701.01