Title
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS
Abstract
In the design of nonvolatile memory (NVM), the sensing scheme (SS) has become a read-energy bottleneck because the required read-cell current is too large to satisfy a target read yield. This problem is further aggravated by technology scaling because increased process variation and reduced supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> ) require more current to satisfy the target read yield. This paper proposes an offset-canceling single-ended SS (OCSE-SS) with one-bit-line precharge architecture (1BLPA) that is intended for use in ultralow power NVM applications. The test chip is fabricated using 65-nm process technology, and the measurement results show that the read energy per bit of the OCSE-SS is 1/3 compared to that of the conventional SS (Conv-SS). The read energy reduction comes from the single-ended sensing, offset cancellation, and 1BLPA features. Moreover, when a resistance difference between the data and reference cells is as small as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5~k\Omega $ </tex-math></inline-formula> , the OCSE-SS reads successfully with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> of 1.0 V and a sensing time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\mathrm {SEN}}$ </tex-math></inline-formula> ) of 17 ns due to the offset cancellation characteristic, whereas the Conv-SS fails regardless of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\mathrm {SEN}}$ </tex-math></inline-formula> values.
Year
DOI
Venue
2019
10.1109/TVLSI.2019.2925931
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
Sensors,Nonvolatile memory,Memory management,Resistance,Very large scale integration,Phase change random access memory
Topology,Computer science,Resistive touchscreen,Voltage,Electronic engineering,Chip,CMOS,Non-volatile memory,Process variation,Very-large-scale integration,Offset (computer science)
Journal
Volume
Issue
ISSN
27
11
1063-8210
Citations 
PageRank 
References 
2
0.39
0
Authors
6
Name
Order
Citations
PageRank
Taehui Na1959.98
Byungkyu Song2235.94
Sara Choi342.17
Jung-Pill Kim410112.78
Seung H. Kang513912.36
Seong-ook Jung633253.74