Title | ||
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10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance |
Abstract | ||
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The paper presents 10 GHz standing wave oscillator (SWO) minimizing distributed capacitance C-d (distributed capacitance generated from multiple cross-coupled pairs (CCP)) for the clock distribution network. The conventional SWOs have been proposed for a negative resistance g(d) (an equivalent transconductance per CCP) to get rid of conductance in RLGC extracted from a transmission line. However, the SWOs have not considered its capacitance. The C-d can not only increase its phase constant but also decrease the unit length of the transmission line. In the proposed SWO, a MOS varactor, C-var(V)(voltage controlled capacitance), is added to minimize c(d)(equivalent capacitance per CCP). To adjust the capacitance of the varactors, the external voltage, V-B, is added. The impedance of the SWO can be represented as 2(- 1/gm1 - 1/gm2 - s1/C-var(V-B) + s1/C-gs3,C-4). The conductance for the proposed design is -4.83mS, which is reduced by 30% compared with the conventional design. The admittance of the capacitance in the proposed design is 3.76 mS while the conventional design has 6.07 mS, which shows approximately 2.29 mS (38 %) reduction. The design is simulated by a 180nm CMOS technology node with 1.8V power supply, and the total power consumption is 5.4 mW for the proposed SWO. |
Year | DOI | Venue |
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2019 | 10.1109/MWSCAS.2019.8885266 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
standing wave oscillator (SWO),negative capacitance,clock distribution network (CDN) | Capacitance,Control theory,Computer science,Atomic physics,Negative resistance,Electrical impedance,Transconductance,Conductance,Admittance,Varicap,Microstrip | Conference |
ISSN | Citations | PageRank |
1548-3746 | 0 | 0.34 |
References | Authors | |
0 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Gyunam Jeon | 1 | 0 | 1.35 |
Yong-bin Kim | 2 | 338 | 55.72 |