Title
Quantum Logic Synthesis with Formal Verification
Abstract
Quantum computers capable of practical information processing are emerging rapidly. As these devices become more advanced, tools will be needed for converting generalized quantum algorithms into formally-verified forms that are executable on real quantum machines. In this work, a prototype tool is presented that transforms quantum algorithms into executable specifications where optimization procedures yield 9-24 % cost improvement on a range of benchmarks. Additionally, the tool incorporates formal verification internally with Quantum Multiple-valued Decision Diagrams to confirm that the generated technology-dependent executable is functionally equivalent to the original, technology-independent algorithm. Experimental results are provided that target the Rigetti family of quantum processing units although the tool may also target other architectures.
Year
DOI
Venue
2019
10.1109/MWSCAS.2019.8885132
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)
Keywords
Field
DocType
quantum information processing,quantum computing,quantum logic synthesis,technology mapping
Quantum,Computer science,Quantum logic,Quantum computer,Electronic engineering,Quantum algorithm,Quantum information science,Qubit,Computer engineering,Formal verification,Executable
Conference
ISSN
ISBN
Citations 
1548-3746
978-1-7281-2789-7
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Kaitlin N. Smith100.34
Mitchell A. Thornton228040.94