Name
Abstract | ||
|---|---|---|
Message passing using a network-on-chip (NoC) is an efficient way to provide core-to-core communication on a multicore processor. However, many NoCs use routers and network interfaces that are optimized for the average case. Therefore, it is hard to bound the worst-case latency of a message or the bandwidth. Furthermore, often large buffers are used in the routers and network interfaces, which require a considerable amount of area.
This paper presents a statically scheduled NoC that uses time-division multiplexing at the links, the routers, and the network interfaces. Static scheduled traffic allows computing upper bounds for end-to-end latencies of messages, which is a requirement for building multicore real-time systems. Furthermore, this static scheduled NoC needs no additional buffers, except pipeline registers, and the resulting resource requirement is low.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3356045.3360714 | Proceedings of the 12th International Workshop on Network on Chip Architectures |
Keywords | Field | DocType |
network-on-chip, real-time systems, time-predictable computer architecture | Computer science,Network on a chip,Distributed computing,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4503-6949-7 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Martin Schoeberl | 1 | 8 | 5.28 |
| luca pezzarossa | 2 | 24 | 4.85 |
| Jens Sparsø | 3 | 453 | 52.97 |