Name
Abstract | ||
|---|---|---|
Hardware security-related threats such as the insertion of malicious circuits, overproduction, and reverse engineering are of increasing concern in the IC industry. To mitigate these threats, various design-for-trust techniques have been developed, including sequential logic locking. Sequential logic locking protects a non-scanned design by employing a key-controlled entrance FSM, key-controlled transitions, or a combination of both techniques. Current methods for characterizing (attacking) the security of sequentially locked circuits do not have the scalability to be applicable to modern circuits. In addition, current methods often require the use of an oracle, which is a working, unlocked circuit that is assumed to be fully initializable and controllable. In this work, an oracle-free, ATPG-based approach is proposed for characterizing the security of a locked sequential circuit. This method is of several in a tool box called CLIC-A (Characterization of Locked ICs via ATPG). Experiments using CLIC-A demonstrate it is effective at recovering the key sequence from various sequentially locked circuits that have been locked using different locking methods. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ITC-Asia.2019.00030 | 2019 IEEE International Test Conference in Asia (ITC-Asia) |
Keywords | Field | DocType |
Hardware Security,Logic Locking,Obfuscation | Automatic test pattern generation,Sequential logic,Hardware security module,Computer science,Reverse engineering,Oracle,Electronic engineering,Computer hardware,Obfuscation,Electronic circuit,Scalability | Conference |
ISBN | Citations | PageRank |
978-1-7281-4719-2 | 1 | 0.36 |
References | Authors | |
10 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Danielle Duvalsaint | 1 | 1 | 0.36 |
| Zeye Liu | 2 | 10 | 3.15 |
| Ananya Ravikumar | 3 | 1 | 0.36 |
| Ronald D. Blanton | 4 | 253 | 26.57 |