Name
Title | ||
|---|---|---|
On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC |
Abstract | ||
|---|---|---|
With the high integration of integrated circuits, small delay faults have occurred as the cause of a circuit failure. We have proposed a method for testing small delay faults using a boundary scan circuit with embedded TDC (TDCBS). In this method, delay faults are detected by using the number of stages in which a transition signal has propagated through a delay line. However, there exists delay variation in a delay line. This paper investigated delay variation by measuring transition delay for different paths in the delay line. In addition, to calibrate delay variation, we investigated a calibration method for considering the variation of wire length and delay in a delay line in TDCBS. Measurement results for an experimental chip show that the method can compensate the variations in the delay line. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ITC-Asia.2019.00042 | 2019 IEEE International Test Conference in Asia (ITC-Asia) |
Keywords | Field | DocType |
small delay fault,boundary scan,TDC,design for-testability | Design for testing,Boundary scan,Circuit Failure,Computer science,Chip,Electronic engineering,Integrated circuit,Calibration | Conference |
ISBN | Citations | PageRank |
978-1-7281-4719-2 | 0 | 0.34 |
References | Authors | |
7 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuya Kikuchi | 1 | 0 | 0.34 |
| Hiroyuki Yotsuyanagi | 2 | 70 | 19.04 |
| Masaki Hashizume | 3 | 98 | 27.83 |