Name
Title | ||
|---|---|---|
A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells |
Abstract | ||
|---|---|---|
Nano-scale CMOS circuits are vulnerable to single-event triple-node-upsets (SETUs). This paper proposes the design of a novel CMOS latch to tolerate any SETU using single-node-upset-resilient cells converged at a highly reliable node. The latch makes use of three single-node-upset-resilient cells, each of which mainly consists of triple mutually feeding back 2-input C-elements. These cells have a common converged output node feeding back to the output of the latch, making the latch capable of tolerating any SETU. Simulation results not only confirm the SETU tolerance capability but also show a significant area-power-delay-product reduction of 96.81% for the proposed latch compared with the only existing SETU hardened latch. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ITC-Asia.2019.00037 | 2019 IEEE International Test Conference in Asia (ITC-Asia) |
Keywords | Field | DocType |
triple node upset,single node upset,hardened latch,C element | Monad (category theory),Computer science,CMOS,Electronic engineering,Upset,Computer hardware,Electronic circuit,C-element | Conference |
ISBN | Citations | PageRank |
978-1-7281-4719-2 | 0 | 0.34 |
References | Authors | |
15 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhiyuan Song | 1 | 0 | 0.34 |
| Aibin Yan | 2 | 29 | 6.78 |
| Jie Cui | 3 | 60 | 11.46 |
| zhili chen | 4 | 44 | 5.88 |
| Xuejun Li | 5 | 34 | 13.95 |
| Xiaoqing Wen | 6 | 790 | 77.12 |
| Chaoping Lai | 7 | 9 | 1.27 |
| Zhengfeng Huang | 8 | 84 | 30.14 |
| Huaguo Liang | 9 | 216 | 33.27 |