Name
Abstract | ||
|---|---|---|
The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5% and 4.2% on average, respectively. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/VLSI-SoC.2019.8920337 | 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) |
Keywords | Field | DocType |
Logic Synthesis,Physical Synthesis,SCCG,Layout Generator | Netlist,Open cell,Computer architecture,Logic gate,Computer science,Design flow,Electronic design automation,Merge (version control),Transistor,Integrated circuit | Conference |
ISSN | ISBN | Citations |
2324-8432 | 978-1-7281-3916-6 | 1 |
PageRank | References | Authors |
0.36 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kevin A. Cáceres Albinagorta | 1 | 1 | 0.36 |
| Calebe Conceição | 2 | 1 | 0.36 |
| Carlos Silva Cárdenas | 3 | 1 | 0.36 |
| Ricardo A. L. Reis | 4 | 217 | 48.75 |