| Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks | 3 | 0.47 | 2021 |
| Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm | 0 | 0.34 | 2021 |
| An Extensive Soft Error Reliability Analysis of a Real Autonomous Vehicle Software Stack | 0 | 0.34 | 2021 |
| Soft Error Reliability Assessment of Neural Networks on Resource-constrained IoT Devices. | 0 | 0.34 | 2020 |
| Security Issues in the Design of Chips for IoT | 0 | 0.34 | 2020 |
| Mitigation Effects of Decoupling Cells on Full Adders Process Variability | 0 | 0.34 | 2020 |
| Contributions to OpenROAD from Abroad - Experiences and Learnings - Invited Paper. | 0 | 0.34 | 2020 |
| Circuit Level Design Methods to Mitigate Soft Errors | 0 | 0.34 | 2020 |
| Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology | 1 | 0.39 | 2020 |
| Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters | 0 | 0.34 | 2020 |
| On the superiority of modularity-based clustering for determining placement-relevant clusters | 0 | 0.34 | 2020 |
| Soft Error Reliability Analysis of Autonomous Vehicles Software Stack | 0 | 0.34 | 2019 |
| Transistor Count Reduction by Gate Merging. | 3 | 0.46 | 2019 |
| Robust FinFET Schmitt Trigger Designs for Low Power Applications. | 0 | 0.34 | 2019 |
| Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability | 0 | 0.34 | 2019 |
| Finding placement-relevant clusters with fast modularity-based clustering. | 0 | 0.34 | 2019 |
| Robustness and Minimum Energy-Oriented FinFET Design | 0 | 0.34 | 2019 |
| Evaluation of SET under Process Variability on FinFET Multi-level Design | 1 | 0.38 | 2019 |
| Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility. | 0 | 0.34 | 2019 |
| Impact of Process Variability and Single Event Transient on FinFET Technology | 0 | 0.34 | 2019 |
| Exploring Schmitt Trigger Circuits for Process Variability Mitigation | 0 | 0.34 | 2019 |
| Netlist Optimization by Gate Merging | 0 | 0.34 | 2019 |
| Exploration of Techniques to Assess Soft Errors in Multicore Architectures | 0 | 0.34 | 2019 |
| Clip Clustering for Early Lithographic Hotspot Classification | 0 | 0.34 | 2019 |
| FinFET Variability and Near-threshold operation - Impact on Full Adders design using XOR Blocks. | 0 | 0.34 | 2019 |
| FBM: A Simple and Fast Algorithm for Placement Legalization | 0 | 0.34 | 2019 |
| Exploring area and total wirelength using a cell merging technique | 1 | 0.36 | 2019 |
| Reducing the amount of transistors by gate merging | 0 | 0.34 | 2018 |
| gem5-FIM: a flexible and scalable multicore soft error assessment framework to early reliability design space explorations | 0 | 0.34 | 2018 |
| Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements | 2 | 0.40 | 2018 |
| A nonlinear placement for FPGAs: The chaotic place | 0 | 0.34 | 2018 |
| Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies. | 0 | 0.34 | 2018 |
| Robustness Of Sub-22nm Multigate Devices Against Physical Variability | 0 | 0.34 | 2017 |
| Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology. | 1 | 0.38 | 2017 |
| Radiation sensitivity of XOR topologies in multigate technologies under voltage variability | 1 | 0.42 | 2017 |
| Process and temperature impact on single-event transients in 28nm FDSOI CMOS | 1 | 0.63 | 2017 |
| Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition. | 0 | 0.34 | 2017 |
| Challenges of cell selection algorithms in industrial high performance microprocessor designs. | 1 | 0.36 | 2016 |
| Improving placement algorithms by using visualization tools | 0 | 0.34 | 2016 |
| Drive Strength Aware Cell Movement Techniques for Timing Driven Placement. | 6 | 0.52 | 2016 |
| Permanent and single event transient faults reliability evaluation EDA tool. | 0 | 0.34 | 2016 |
| Routing-Aware Incremental Timing-Driven Placement | 1 | 0.36 | 2016 |
| Reducing the number of transistors with gate clustering | 2 | 0.42 | 2016 |
| Cell Selection for High-Performance Designs in an Industrial Design Flow. | 3 | 0.40 | 2016 |
| Leakage current analysis in static CMOS logic gates for a transistor network design approach | 0 | 0.34 | 2016 |
| Efficient emulation of quantum circuits on classical hardware | 0 | 0.34 | 2015 |
| Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability | 0 | 0.34 | 2015 |
| Impact of dynamic voltage scaling and thermal factors on SRAM reliability | 1 | 0.39 | 2015 |
| Energy-efficient Level Shifter topology | 0 | 0.34 | 2015 |
| A Mixed Cells Physical Design Approach | 0 | 0.34 | 2015 |
