Title
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors
Abstract
High-performance superscalar processors have been adopted to satisfy the rising demand for processing applications of ever-growing complexity. This extra complexity, added to the increasing vulnerability of transistors due to technology scaling, poses a great challenge since these effects have also been proven to affect ground-level safety-critical applications. To increase microarchitectural resilience, designers may adopt Dual Modular Redundancy (DMR), which offers full fault detection. However, given that DMR incurs in high area and energy overheads, we propose a design-time methodology aiming to achieve the best tradeoff between resilience and area overhead, decreasing DMR costs and maintaining acceptable detection levels for such a complex design. This is done by adopting the Knapsack Problem (KSP) as a heuristic to identify the optimal micro-architectural structures that should be duplicated to achieve target resilience with the smallest possible area overhead. By injecting over 800k faults in 12 significant micro-architectural structures of different versions of the complex Berkeley Out-of-Order Machine (BOOM) superscalar processor modeled with RTL accuracy, we compare this optimal strategy against a greedy one, showing that 90% of vulnerability reduction may be achieved with 50.6% and 107.8% area overheads for the optimal and greedy strategies, respectively.
Year
DOI
Venue
2019
10.1109/VLSI-SoC.2019.8920350
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
Keywords
Field
DocType
Fault tolerance,RTL design,out-of-order superscalar reliability
Psychological resilience,Heuristic,Fault detection and isolation,Computer science,Dual modular redundancy,Knapsack problem,Boom,Out-of-order execution,Embedded system,Overhead (business)
Conference
ISSN
ISBN
Citations 
2324-8432
978-1-7281-3916-6
0
PageRank 
References 
Authors
0.34
10
7