Title
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS
Abstract
This article describes a 128-Gb/s pulse amplitude-modulation 4-level (PAM-4) transmitter (TX) implemented in a 14-nm CMOS FinFET technology. Equalization is provided by a fully reconfigurable 3-tap baud-spaced feed-forward equalizer (FFE). The TX uses a segmented tailless current mode logic (CML) driver topology. The key architectural and circuit techniques include the thermometer-encoded driver slices, the clock phase selection circuits to perform segment reassignment to different FFE taps, and coarse–fine tuning of the FFE tap weights. The measured energy efficiencies for PAM-4 signaling are 1.33 pJ/b at 128 Gb/s with 1-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ppd</sub> output amplitude and 1.0 pJ/b at 112 Gb/s with 0.6-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ppd</sub> output amplitude. These results represent the highest data rate and best energy efficiencies reported to date.
Year
DOI
Venue
2020
10.1109/JSSC.2019.2939081
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Clocks,Optical signal processing,Transmitters,Bandwidth,Topology,Integrated circuit modeling,Capacitance
Transmitter,Equalization (audio),Computer science,Pulse (signal processing),Electronic engineering,CMOS,Data rate,Current-mode logic,Electronic circuit,Amplitude
Journal
Volume
Issue
ISSN
55
1
0018-9200
Citations 
PageRank 
References 
0
0.34
0
Authors
7