Name
Abstract | ||
|---|---|---|
An automated circuit sizing approach is presented, that uses the inversion coefficient to constrain each transistor in the desired inversion region. An analytical expression for the inversion coefficient based on the BSIM4 model is presented. The inversion coefficient of each transistor is calculated from the simulation results, transistor design parameters and technology model parameters. The optimization approach is illustrated on a folded-cascode operational amplifier. Each individual transistor is constrained in a specific inversion region, based on its requirements for gain, speed and matching. The consideration of inversion constraints speeds up the yield optimization. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ICECS46596.2019.8965193 | 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) |
Keywords | Field | DocType |
specific inversion region,inversion constraints,inversion-coefficient-aware yield optimization,analog circuits,automated circuit sizing approach,inversion coefficient,BSIM4 model,transistor design parameters,technology model parameters,optimization approach,folded-cascode operational amplifier | Analogue electronics,Computer science,Circuit sizing,Inversion (meteorology),Electronic engineering,Transistor,Transistor design,Operational amplifier | Conference |
ISBN | Citations | PageRank |
978-1-7281-0997-8 | 0 | 0.34 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Florin Burcea | 1 | 0 | 0.34 |
| Helmut E. Graeb | 2 | 269 | 36.22 |