Name
Abstract | ||
|---|---|---|
This paper evaluates the potential of using the sleep transistor in FinFET logic cells to mitigate the process variability effects and the soft error susceptibility. The insertion of a sleep transistor improves up to 40.6% the delay variability and up to 12.4% the power variability. Moreover, the design with a sleep transistor became all logic cells investigated free of faults, independently of the supply voltage applied in the design. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ICECS46596.2019.8965045 | ICECS |
Field | DocType | Citations |
Soft error,Microelectronics,Computer science,Voltage,Electronic engineering,Transistor,Process variability | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexandra L. Zimpeck | 1 | 0 | 0.34 |
| Cristina Meinhardt | 2 | 21 | 13.35 |
| Laurent Artola | 3 | 0 | 0.68 |
| Guillaume Hubert | 4 | 0 | 0.68 |
| Fernanda Lima Kastensmidt | 5 | 554 | 61.82 |
| Ricardo A. L. Reis | 6 | 217 | 48.75 |