Name
Abstract | ||
|---|---|---|
Routing closure and design-for-manufacturability (DFM) challenges exacerbate nonrecurring engineering (NRE) costs, a steep barrier to entry for advanced sub-20-nm CMOS nodes, making low-volume fabrication of integrated circuits (ICs) almost intangible. For ICs in which the cost of design dominates the fabrication, we seek to trade some amount of chip area to lower NRE costs. To this end, we consid... |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TVLSI.2019.2942825 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Pins,Routing,Layout,Computer architecture,Microprocessors,Libraries | Computer architecture,Computer science,Electronic engineering,CMOS,Integrated circuit design | Journal |
Volume | Issue | ISSN |
28 | 2 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mehmet Meric Isgenc | 1 | 3 | 2.41 |
| Mayler G. A. Martins | 2 | 88 | 10.08 |
| V. Mohammed Zackriya | 3 | 0 | 0.68 |
| Samuel N. Pagliarini | 4 | 14 | 4.96 |
| Lawrence T. Pileggi | 5 | 9 | 2.71 |