Name
Title | ||
|---|---|---|
Variation Analysis Of Interconnect Capacitance And Process Corner In Advanced Cmos Process With Double Patterning Technology |
Abstract | ||
|---|---|---|
Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ASICON47005.2019.8983474 | 2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) |
Field | DocType | ISSN |
Capacitance,Parasitic capacitance,Computer science,Double patterning lithography,Process corners,Electronic engineering,Cmos process,Multiple patterning,Overlay,Interconnection,Optoelectronics | Conference | 2162-7541 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhimei Cai | 1 | 0 | 0.68 |
| Zhiyong Han | 2 | 0 | 0.34 |
| Ming Tian | 3 | 0 | 1.01 |
| Changfeng Wang | 4 | 0 | 0.34 |
| Xiaoming Hu | 5 | 0 | 0.34 |
| Ran Cheng | 6 | 0 | 0.68 |
| Yi Zhao | 7 | 1 | 1.71 |