Paper Info
Title
A Novel Signed Bit-serial Fixed-point Accumulator with Configurable Overflow-Protection Precision
Abstract
In the design of digital signal arithmetic circuits, the serial structure is widely used because of its high clock frequency, low power and area consumption. The bit-serial accumulator is the basic arithmetic unit used in the serial systems, and also the key unit for the performance of the whole system. For the requirements of a bit-serial accumulator for general digital signal processing (DSP) systems and machine learning (ML) algorithms, a novel scheme of the signed bit-serial fixed-point accumulator is proposed in this paper. For the overflow issue, an overflow-protection circuit with configurable precision is provided as the main contribution of the proposed scheme, which can achieve the tradeoff between accuracy and latency for the signed system design. In the case study, the proposed scheme is applied to the convolution operations in convolutional neural networks (CNNs). The experimental results show that the proposed scheme can achieve a good implementation performance with reconfigurability.
Year
DOI
Venue
2019
10.1109/ASICON47005.2019.8983432
2019 IEEE 13th International Conference on ASIC (ASICON)
Keywords
Field
DocType
serial structure,high clock frequency,bit-serial accumulator,basic arithmetic unit,serial systems,overflow issue,overflow-protection circuit,configurable precision,signed system design,configurable overflow-protection precision,digital signal arithmetic circuits,signed bit-serial fixed-point accumulator
Digital signal processing,Reconfigurability,Convolutional neural network,Computer science,Digital signal,Convolution,Systems design,Electronic engineering,Computer hardware,Accumulator (structured product),Clock rate
Conference
ISSN
ISBN
Citations 
2162-7541
978-1-7281-0736-3
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
Lin Li132379.92
Qiu Huang200.34
Hu Jianhao39620.56
Jienan Chen48413.64