Name
Title | ||
|---|---|---|
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth |
Abstract | ||
|---|---|---|
The last two decades have witnessed a large number of proposals on the last-level cache (LLC) replacement policy aiming to minimize the number of LLC read misses. Another independent large body of work has explored mechanisms to address the inefficiencies arising from the DRAM writes introduced by the LLC replacement policy. These DRAM scheduling proposals, however, leave the LLC replacement policy unchanged and, as a result, miss the opportunity of synergistically shaping and scheduling the DRAM write bandwidth demand. In this paper, we argue that DRAM read and write bandwidth demands must be coordinated carefully from the LLC side and hence, introduce bandwidth-awareness in the LLC policy. Our bandwidth-aware LLC policy proposal enables long uninterrupted stretches of DRAM reads while maintaining the efficiency of the last-level cache and controlling precisely when and for how long writes can demand DRAM bandwidth. Our proposal comfortably outperforms the state-of-the-art eager DRAM write scheduling proposals and bridges 75% of the performance gap between the baseline and a hypothetical system that deploys an unbounded DRAM write buffer. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ICCD46524.2019.00022 | 2019 IEEE 37th International Conference on Computer Design (ICCD) |
Keywords | Field | DocType |
DRAM bandwidth, Last-level caching, DRAM writes | Dram,Computer science,Scheduling (computing),Cache,Parallel computing,Computer network,Chip,Write buffer,Bandwidth (signal processing),Performance gap | Conference |
ISSN | ISBN | Citations |
1063-6404 | 978-1-7281-1215-2 | 0 |
PageRank | References | Authors |
0.34 | 45 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mainak Chaudhuri | 1 | 300 | 18.86 |
| Jayesh Gaur | 2 | 108 | 6.98 |
| Sreenivas Subramoney | 3 | 127 | 13.60 |