Paper Info
Title
Safety Design of a Convolutional Neural Network Accelerator with Error Localization and Correction
Abstract
Recently neural network accelerators have grown into prominence with significant power and performance efficiency improvements over CPU and GPU. In this paper, we proposed two safety design techniques include Algorithm Based Atomic Error Checking-1 (ABAEC-1) and ABAEC-2 for a Weight Stationary (WS) Convolutional Neural Network (CNN) accelerator focusing on low latency and low overhead error detection and correction with no performance degradation. The proposed design techniques not only detect the errors on-the-fly but also perform error diagnosis to localize the errors to a Processing Element (PE) for on-line fault management and recovery. We applied the design techniques on an industry quality CNN accelerator and demonstrated that we could achieve the required Diagnostic Coverage (DC) goal with minimal area and power overhead for selected configurations. Furthermore, we discussed methods to extend the proposed techniques to other dataflow architecture.
Year
DOI
Venue
2019
10.1109/ITC44170.2019.9000149
2019 IEEE International Test Conference (ITC)
Keywords
Field
DocType
safety design techniques,ABAEC-2,error detection,performance degradation,error diagnosis,on-line fault management,industry quality CNN accelerator,power overhead,error localization,neural network accelerators,weight stationary convolutional neural network accelerator,algorithm based atomic error checking-1,CPU,GPU,diagnostic coverage,processing element,PE
Dataflow architecture,Performance efficiency,Computer science,Convolutional neural network,Real-time computing,Fault management,Error detection and correction,Safety design,Latency (engineering),Artificial neural network,Computer engineering
Conference
ISSN
ISBN
Citations 
1089-3539
978-1-7281-4824-3
0
PageRank 
References 
Authors
0.34
12
2
Name
Order
Citations
PageRank
Zheng Xu1187.58
Jacob A. Abraham261.72