Paper Info
Title
A Framework for Design of Self-Repairing Digital Systems
Abstract
This paper introduces a scalable framework for the design of self-testable, self-correcting, and self-repairing digital systems. Modular redundancy and re-programmability are used to accomplish generic self-test and to enable self-repair. Bit error rates (BER) are measured throughout the design to distinguish between transient errors and errors due to semi- or permanent-logic faults. Tri-modular redundancy (TMR) is used for error correction and fault-isolation with a fourth module available for automated repair. Modular reconfiguration (repair) occurs automatically, so that the system continues to operate error-free even during partial dynamic reconfiguration (in FPGAs). The state of a repaired module is re-synchronized with the running system within one cycle after the damaged module is replaced. The framework is capable of simultaneous repair of multiple faults, while ensuring error-free operation. A case study evaluates the reliability improvement of an FPGA-based neural network image classification application.
Year
DOI
Venue
2019
10.1109/ITC44170.2019.9000155
2019 IEEE International Test Conference (ITC)
Keywords
Field
DocType
image classification,FPGA-based neural network,partial dynamic reconfiguration,self-correcting digital systems,design of self-testable system,error-free operation,modular reconfiguration,fault-isolation,error correction,tri-modular redundancy,permanent-logic faults,transient errors,bit error rates,self-repairing digital systems
Computer science,Field-programmable gate array,Real-time computing,Error detection and correction,Redundancy (engineering),Modular design,Artificial neural network,Computer hardware,Contextual image classification,Control reconfiguration,Scalability
Conference
ISSN
ISBN
Citations 
1089-3539
978-1-7281-4824-3
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Jingchi Yang100.34
David C. Keezer26817.00