Name
Abstract | ||
|---|---|---|
In-Memory Computing (IMC) architectures based on Static Random Access Memory (SRAM) can improve system performance and energy-efficiency dramatically. However, most of the existing SRAM-based implementations are designed for specific purposes like accelerating neural networks, which limits the application scenarios of IMC. In this paper, we propose DM-LMCA, a novel LAC architecture with two work modes for general purpose processing. It utilizes our proposed 9T bitcell based computational SRAM as the location to perform LAIC operations. Besides, a new IMC Instruction Set Architecture (ISA) as well as an automated vector computing mechanism are also proposed to facilitate DM-IMCA's programming and accelerate in-memory computing, respectively. The simulation results show that DM-LMCA can bring a performance increase by up to 257x, and SRAM energy saving by up to 3x, compared to a baseline system. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1587/elex.17.20200005 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
Processing-In-Memory (PIM), In-Memory Computing (IMC), Logic-in-Memory (LiM), computational SRAM, data-intensive computing, vector computing | Architecture,Computer architecture,Data-intensive computing,General purpose,Computer science,In-Memory Processing,Electronic engineering | Journal |
Volume | Issue | ISSN |
17 | 4 | 1349-2543 |
Citations | PageRank | References |
1 | 0.40 | 0 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jianmin Zeng | 1 | 1 | 0.40 |
| Zhang Zhang | 2 | 5 | 8.09 |
| Runhao Chen | 3 | 1 | 0.40 |
| Shiyue Liang | 4 | 1 | 0.40 |
| Tianlin Cao | 5 | 31 | 2.50 |
| Zhiyi Yu | 6 | 81 | 18.24 |
| Xin Cheng | 7 | 1 | 0.40 |
| Guangjun Xie | 8 | 29 | 9.64 |