Abstract | ||
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Field-programmable gate arrays (FPGAs) have become a popular compute platform for convolutional neural network (CNN) inference; however, the design of a CNN model and its FPGA accelerator has been inherently sequential. A CNN is first prototyped with no-or-little hardware awareness to attain high accuracy; subsequently, an FPGA accelerator is tuned to that specific CNN to maximize its efficiency. Instead, we formulate a neural architecture search (NAS) optimization problem that contains parameters from both the CNN model and the FPGA accelerator, and we jointly search for the best CNN model-accelerator pair that boosts accuracy and efficiency -we call this Codesign-NAS. In this paper we focus on defining the Codesign-NAS multiobjective optimization problem, demonstrating its effectiveness, and exploring different ways of navigating the codesign search space. For Cifar-10 image classification, we enumerate close to 4 billion model-accelerator pairs, and find the Pareto frontier within that large search space. Next we propose accelerator innovations that improve the entire Pareto frontier. Finally, we compare to ResNet on a highly-tuned accelerator, and show that using codesign, we can improve on Cifar-100 classification accuracy by 1.8% while simultaneously increasing performance/area by 41% in just 1000 GPU-hours of running Codesign-NAS, thus demonstrating that our automated codesign approach is superior to sequential design of a CNN model and accelerator.
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Year | DOI | Venue |
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2020 | 10.1145/3373087.3375334 | FPGA |
Field | DocType | ISBN |
Computer architecture,Architecture,Computer science,Parallel computing,Field-programmable gate array | Conference | 978-1-4503-7099-8 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 |
Name | Order | Citations | PageRank |
---|---|---|---|
Mohamed S. Abdelfattah | 1 | 144 | 13.65 |
Łukasz Dudziak | 2 | 17 | 4.37 |
Thomas C. P. Chau | 3 | 7 | 2.64 |
Royson Lee | 4 | 8 | 2.85 |
Kim, Hyeji | 5 | 23 | 6.94 |
Nicholas D. Lane | 6 | 4247 | 248.15 |