Name
Abstract | ||
|---|---|---|
Clockless integrated circuits, as any type of integrated system, might today carry hardware Trojan (HT) circuits maliciously implanted in the designs during outsourced phases of fabrication. This paper proposes a testing technique dedicated to detect HTs in clockless circuits fabricated in CMOS technologies. The proposed technique applies a well-known machine learning approach – One-Class Support Vector Machine (OC-SVM) – for dealing with the particular current signature features of clockless circuits. Through simulation experiments we show the natural ability of clockless circuits in providing individual current signatures for identifying the presence of HTs. Moreover, the results demonstrate that our testing technique requires no extra circuitry or power ports to detect HTs of a few dozens of transistors in designs under Trojan test with more than 13 thousand transistors. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1007/s10836-020-05857-6 | Journal of Electronic Testing |
Keywords | DocType | Volume |
Hardware trojans, Clockless circuits, Asynchronous circuits, Machine learning, Support vector machine, Current signature, Transient current, Trojan detection, Side channel, Quasi-delay insensitive | Journal | 36 |
Issue | ISSN | Citations |
1 | 0923-8174 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ricardo Aquino Guazzelli | 1 | 0 | 0.34 |
| Matheus Garay Trindade | 2 | 0 | 0.34 |
| Leonel Acunha Guimaraes | 3 | 3 | 1.43 |
| Thiago Ferreira de Paiva Leite | 4 | 1 | 2.05 |
| Laurent Fesquet | 5 | 289 | 49.04 |
| Rodrigo Possamai Bastos | 6 | 80 | 13.80 |