Paper Info
Title
Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation
Abstract
The paper presents standing wave oscillator-based clock distribution minimizing equivalent capacitance (c <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ) for process and temperature variation. The SWOs have been proposed to enhance the negative resistance g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> (an equivalent transconductance per ccp) to cancel the conductance in a transmission line. However, the SWOs have a parasitic capacitance which affects clock phase and unit length of the transmission line. In the proposed SWO, a MOS varactor, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">var</sub> (V) (voltage-controlled capacitance), is added to minimize c <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> (equivalent capacitance per ccp). A phase locked loop and other peripherals are added to adjust the frequency and c <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> because the target frequency in the SWO varies due to process and temperature variation The design is simulated by a 180nm CMOS technology node with 1.8V power supply, and the total power consumption is 31.841 mW for the proposed architecture.
Year
DOI
Venue
2019
10.1109/ISOCC47750.2019.9027698
2019 International SoC Design Conference (ISOCC)
Keywords
DocType
ISSN
cross-coupled pair (ccp),standing wave oscillator,negative impedance converter (NIC)
Conference
2163-9612
ISBN
Citations 
PageRank 
978-1-7281-2479-7
0
0.34
References 
Authors
1
3
Name
Order
Citations
PageRank
Gyunam Jeon101.35
Kyung Ki Kim29921.62
Yong-Bin Kim300.68