A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. - Citegraph

Paper Info

Title
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer.

Year	DOI	Venue
2019	10.1007/978-3-030-37277-4_59	ApplePies
DocType	Citations	PageRank
Conference	2	0.44
References	Authors
0	6

Authors (6 rows)

Cited by (2 rows)

References (0 rows)

Name	Order	Citations	PageRank
Luigi Blasi	1	2	0.44
Francesco Vigli	2	2	0.44
Abdallah Cheikh	3	2	0.78
Antonio Mastrandrea	4	2	1.46
Francesco Menichelli	5	2	0.78
Mauro Olivieri	6	385	36.09

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