Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. - Citegraph

Paper Info

Title
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor.

Year	DOI	Venue
2019	10.1007/978-3-030-37277-4_62	ApplePies
DocType	Citations	PageRank
Conference	0	0.34
References	Authors
0	5

Authors (5 rows)

Cited by (0 rows)

References (0 rows)

Name	Order	Citations	PageRank
Abdallah Cheikh	1	2	0.78
Stefano Sordillo	2	0	0.34
Antonio Mastrandrea	3	2	1.46
Francesco Menichelli	4	2	0.78
Mauro Olivieri	5	385	36.09

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