Name
Title | ||
|---|---|---|
Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications. |
Abstract | ||
|---|---|---|
A Digital Annealer (DA) is a dedicated architecture for high-speed solving of combinatorial optimization problems mapped to an Ising model. With fully coupled bit connectivity and high coupling resolution as a major feature, it can be used to express a wide variety of combinatorial optimization problems. The DA uses Markov Chain Monte Carlo as a basic search mechanism, accelerated by the hardware implementation of multiple speed-enhancement techniques such as parallel search, escape from a local solution, and replica exchange. It is currently being offered as a cloud service using a second-generation chip operating on a scale of 8,192 bits. This paper presents an overview of the DA, its performance against benchmarks, and application examples. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ASP-DAC47756.2020.9045100 | ASP-DAC |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satoshi Matsubara | 1 | 0 | 0.34 |
| Motomu Takatsu | 2 | 2 | 0.72 |
| Toshiyuki Miyazawa | 3 | 2 | 1.73 |
| Takayuki Shibasaki | 4 | 66 | 12.00 |
| Yasuhiro Watanabe | 5 | 0 | 0.34 |
| Kazuya Takemoto | 6 | 2 | 0.72 |
| Hirotaka Tamura | 7 | 204 | 32.19 |