Paper Info
Title
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST.
Abstract
There is enormous demand for high-bandwidth DRAM: in application such as HPC, graphics, high-end server and artificial intelligence. HBM DRAM was developed [1] using the advances in package technology: TSV, microbump and silicon-interposer. Owing to these advances, HBM has a much higher bandwidth, at a lower pin speed rate, than conventional DRAM. However, the 3D-stack structure causes TSV interface and PDN problems: TSV connection failure and 3D-accumulation of IR drop, which increases the total cost of HBM. Moreover, as memory bandwidth increases DRAM architectural challenges arise, power consumption and associated thermal problems increase as well.
Year
DOI
Venue
2020
10.1109/ISSCC19947.2020.9062977
ISSCC
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
0
37
Name
Order
Citations
PageRank
Dong Uk Lee1807.98
Ho Sung Cho221.48
Jihwan Kim3173.64
Young Jun Ku421.14
Sangmuk Oh521.48
Chul Dae Kim600.34
Hyun Woo Kim76312.99
Woo-Young Lee8135.96
Tae-Kyun Kim91987129.30
Tae Sik Yun1021.14
Minjeong Kim1143550.98
SeungGyeon Lim1200.34
Seong Hee Lee1341.65
Byung Kuk Yun1400.34
Jun Il Moon1500.34
Ji Hwan Park1600.68
Seokwoo Choi1702.03
young jun park18485.45
Chang Kwon Lee1900.68
Chun-Seok Jeong20194.20
Jae-Seung Lee2100.68
Sang Hun Lee2200.34
Woo Sung We2300.34
Jong Chan Yun2400.68
Doobock Lee2500.34
Junghyun Shin2600.34
Seungchan Kim2700.34
Junghwan Lee2800.34
Jiho Choi2900.34
Yucheon Ju3000.34
Myeong-Jae Park3100.68
Kang Seol Lee32222.65
Youngdo Hur3300.68
Daeyong Shim34111.76
Sangkwon Lee35102.82
Junhyun Chun3622.42
Kyowon Jin3701.01