Name
Title | ||
|---|---|---|
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions |
Abstract | ||
|---|---|---|
Combinatorial optimization problems ubiquitously appear in AI applications, e.g. machine learning, operational planning, drug discovery, etc. Yet, their NP-hardness makes them notoriously difficult to solve on present computers. To address this problem, new hardware architectures [1, 4], called annealers, have emerged in recent years. Annealers exploit the fact that combinatorial optimization problems can be mapped to the ground state search of an Ising model, where the combination of N spins (σ- ∈ f-1}. x=1, ...,N) with lowest Ising energy represents the optimal solution to the problem (Fig. 7.3.1). |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ISSCC19947.2020.9062965 | 2020 IEEE International Solid- State Circuits Conference - (ISSCC) |
Keywords | DocType | ISSN |
hardware architectures,NP-hardness,drug discovery,operational planning,machine learning,complete spin-spin interactions,all-spin-updates-at-once architecture,full-digital annealing processor,512-Spin 0.25M-weight,optimal solution,combinatorial optimization problems | Conference | 0193-6530 |
ISBN | Citations | PageRank |
978-1-7281-3206-8 | 1 | 0.43 |
References | Authors | |
1 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kasho Yamamoto | 1 | 3 | 1.97 |
| Kota Ando | 2 | 24 | 6.81 |
| Normann Mertig | 3 | 3 | 1.63 |
| Takashi Takemoto | 4 | 1 | 0.77 |
| Masanao Yamaoka | 5 | 128 | 23.39 |
| Hiroshi Teramoto | 6 | 3 | 2.64 |
| Akira Sakai | 7 | 3 | 1.63 |
| Shinya Takamaeda-Yamazaki | 8 | 65 | 16.83 |
| Masato Motomura | 9 | 8 | 3.65 |