Shinya Takamaeda-Yamazaki

Author Info

Name	Affiliation	Papers
SHINYA TAKAMAEDA-YAMAZAKI	Graduate School of Information Science and Engineering, Tokyo Institute of Technology and JSPS Research Fellow	42
Collaborators	Citations	PageRank
76	65	16.83
Referers	Referees	References
257	516	152

Search Limit

100516

Publications (42 rows)

Collaborators (76 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark	0	0.34	2022
ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design	0	0.34	2021
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS	2	0.39	2021
An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising	0	0.34	2021
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions	2	0.52	2021
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs.	1	0.35	2020
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions	1	0.43	2020
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA	0	0.34	2020
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes	0	0.34	2020
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS	3	0.44	2019
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators	0	0.34	2019
Fpga-Based Annealing Processor With Time-Division Multiplexing	0	0.34	2019
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band	0	0.34	2019
DeltaNet: Differential Binary Neural Network	0	0.34	2019
Dither Nn: Hardware/Algorithm Co-Design For Accurate Quantized Neural Networks	0	0.34	2019
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.	0	0.34	2018
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.	15	0.85	2018
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA.	1	0.40	2018
A Tree-Based Checkpointing Architecture For The Dependability Of Fpga Computing	1	0.67	2018
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators	0	0.34	2018
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware	1	0.43	2018
Accelerating deep learning by binarized hardware.	0	0.34	2017
In-memory area-efficient signal streaming processor design for binary neural networks	1	0.38	2017
CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing	0	0.34	2017
A Time-Division Multiplexing Ising Machine on FPGAs.	0	0.34	2017
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training	0	0.34	2017
CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing	0	0.34	2016
Performance Optimization Of Light-Field Applications On Gpu	1	0.36	2016
CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis	0	0.34	2016
Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs	1	0.35	2016
A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations.	0	0.34	2015
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators	2	0.40	2015
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL.	8	0.50	2015
Ultrasmall: A Tiny Soft Processor Architecture With Multi-Bit Serial Datapaths For Fpgas	2	0.39	2015
A CGRA-Based Approach for Accelerating Convolutional Neural Networks	6	0.52	2015
Ultrasmall: The smallest MIPS soft processor	4	0.57	2014
A framework for efficient rapid prototyping by virtually enlarging FPGA resources	2	0.43	2014
flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms	3	0.45	2014
ScalableCore system: a scalable many-core simulator by employing over 100 FPGAs	3	0.43	2012
Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations	2	0.38	2012
An FPGA-based scalable simulation accelerator for tile architectures	3	0.45	2011
Smart Core System for Dependable Many-Core Processor with Multifunction Routers	0	0.34	2010