Paper Info
Title
Fpga Fabric Conscious Design And Implementation Of Speed-Area Efficient Signed Digit Add-Subtract Logic Through Primitive Instantiation
Abstract
This paper addresses efficient Field Programmable Gate Array (FPGA) implementations of radix-2 and radix4 signed digit add-subtract architectures. The circuits have been realized by instantiating physical FPGA primitives and configuring them appropriately to obtain speed-area efficient realizations. Underutilized, yet configured logic primitives are targeted to reduce logic levels for certain implementations or append fault detection logic, such as alternating logic through self dual duplication, using a design automation framework. Simple C programs with linear computational complexity carries out the automation. Our proposed implementation outperforms architectures synthesized through behavioral modeling, or original architectures appended with state-of-the-art FPGA centric error-detection strategies, both in speed and area.
Year
DOI
Venue
2019
10.1109/IEEECONF44664.2019.9049071
CONFERENCE RECORD OF THE 2019 FIFTY-THIRD ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS
Keywords
DocType
ISSN
FPGA, signed digit adder, Look-Up Table, carry chain, primitive instantiation, alternating logic
Conference
1058-6393
Citations 
PageRank 
References 
0
0.34
0
Authors
2
Name
Order
Citations
PageRank
Ayan Palchaudhuri1117.67
Anindya Sundar Dhar29726.09