Paper Info
Title
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions
Abstract
Vector processors offer a wide range of unexplored opportunities to improve performance and energy efficiency. However, despite its potential, vector code generation and execution have significant challenges, the most relevant ones being control flow divergence. Most modern processors including SIMD extensions (such as AVX) rely on predication to support divergence control. In predicated codes, performance and energy consumption are usually insensitive to the number of true values in a predicated mask. This implies that the system efficiency becomes sub-optimal as vector length increases. In this paper we focus on SIMD extensions and propose a novel approach to improve execution efficiency in predicated SIMD instructions, the Compaction/Restoration (CR) technique. CR delays predicated SIMD instructions with inactive elements and compacts them with instances of the same instruction from different loop iterations to form an equivalent dense vector instruction, where, in the best case, all the elements are active. After executing such dense instructions, their results are restored to the original instructions. Our evaluation shows that CR improves performance by up to 25% and reduces dynamic energy consumption by up to 43% on real unmodified applications with predicated execution. Moreover, CR allows executing unmodified legacy code with short vector instructions (AVX-2) on newer architectures with wider vectors (AVX-512), achieving up to 56% performance benefits.
Year
DOI
Venue
2020
10.1109/HPCA47549.2020.00064
2020 IEEE International Symposium on High Performance Computer Architecture (HPCA)
Keywords
DocType
ISSN
SIMD,Energy effiency,Predication
Conference
1530-0897
ISBN
Citations 
PageRank 
978-1-7281-6150-1
0
0.34
References 
Authors
18
5
Name
Order
Citations
PageRank
Adrian Barredo102.37
Juan Manuel Cebrian22410.19
Miquel Moretó320525.49
Marc Casas411123.61
Mateo Valero54520355.94