Name
Title | ||
|---|---|---|
A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC |
Abstract | ||
|---|---|---|
We present a single-bit continuous-time delta-sigma ADC that achieves 82.1 dB peak SNDR and 101.2 dB SFDR in a 65 nm CMOS process. The modulator, which operates with a sampling rate of 2.56 GHz, uses a 2x time-interleaved single-bit ADC in the loop. The key technique that enables low distortion is the use of a virtual-ground-switched resistive FIR feedback DAC, which operates in a 4x time-interleaved manner to reduce power dissipation. Interleaving artifacts, caused by mismatch, are addressed by mixed-signal calibration. The decimator is realized using polyphase techniques. The modulator and decimator consume 11.4mW and 15mW from a 1.1 V supply respectively. The Schreier FoM is 174.1 dB. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/CICC48029.2020.9075946 | 2020 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | DocType | ISSN |
time-interleaved single-bit ADC,virtual-ground-switched resistive FIR feedback DAC,continuous-time delta-sigma ADC,time-interleaved virtual-ground-switched FIR feedback DAC,CMOS process,power dissipation,mixed-signal calibration,polyphase techniques,size 65.0 nm,power 15.0 mW,frequency 2.56 GHz,power 11.4 mW,voltage 1.1 V,frequency 20.0 MHz | Conference | 0886-5930 |
ISBN | Citations | PageRank |
978-1-7281-6032-0 | 0 | 0.34 |
References | Authors | |
1 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alok Baluni | 1 | 0 | 0.34 |
| Shanthi Pavan | 2 | 391 | 87.81 |