Name
Abstract | ||
|---|---|---|
Monolithic 3-D (M3D) technology enables unprecedented degrees of integration on a single chip. The miniscule monolithic intertier vias (MIVs) in M3D are the key behind higher transistor density and more flexibility in designing circuits compared to conventional through silicon via (TSV)-based architectures. This article presents a comprehensive design and test techniques for emerging M3D-enabled circuits and systems. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/MDAT.2020.2988657 | IEEE Design & Test |
Keywords | DocType | Volume |
monolithic 3D,MIV,EDA,Shrunk-2D,design-for-test,BIST,resistive defect,ReRAM,ReRAM compiler,design-space exploration | Journal | 37 |
Issue | ISSN | Citations |
4 | 2168-2356 | 1 |
PageRank | References | Authors |
0.38 | 0 | 10 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arjun Chaudhuri | 1 | 17 | 7.07 |
| Sanmitra Banerjee | 2 | 9 | 4.68 |
| Heechun Park | 3 | 13 | 5.44 |
| Jinwoo Kim | 4 | 1 | 3.08 |
| Gauthaman Murali | 5 | 4 | 3.27 |
| Edward Lee | 6 | 4 | 3.79 |
| Dae Hyun Kim | 7 | 505 | 46.95 |
| Sung Kyu Lim | 8 | 1688 | 168.71 |
| Saibal Mukhopadhyay | 9 | 1288 | 150.52 |
| K Chakrabarty | 10 | 8173 | 636.14 |