Name
Title | ||
|---|---|---|
Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing |
Abstract | ||
|---|---|---|
An adaptive routing helps in evading early network saturation by steering data packets through the less congested area at the oppressive loaded situation. However, performances of adaptive routing are not always promising under all circumstances. Say for, given more freedom in choosing an alternate route on non-minimal paths for a substantially loaded network even may result in worsening network performances due to following longer route under adaptive routing. Here, underlying topology facilitates routing by offering more alternate short-cut routes on minimal or quasi-minimal paths. This work presents a congestion-aware (CA) adaptive routing for one-hop diagonally connected subnet-based mesh (SDmesh) network aiming to facilitate both performances and routing flexibility simultaneously. Our proposed technique on the selected system facilitates packet routing, offering more options in choosing an output link from minimal or quasi-minimal paths and hence helps in lowering packet delay by shortening the length of traversed traffic under the oppressive loaded situation. Furthermore, we have also employed a congestion-aware virtual input crossbar router aiming to split the entire network into two distinct logically separated sub-networks. It facilitates preserving important routing properties like deadlock, live-lock fairness, and other essential routing constraints. Experiments, conducted over two 8×8- and 12×12-sized networks, show an average improvement of 25--87.5% saturated latency and 60--83% throughput improvement under uniform traffic patterns for the proposed CA routing compared to centralized adaptive XY routing. Experimental results on application-specific PARSEC and SPLASH2 benchmark suites show an average of 22--50% latency and 23--30% throughput improvements by the proposed technique compared to centralized XY routing on the baseline mesh network. Moreover, experiments were also carried out to check the performance of the proposed routing method with different newly proposed deadlock-free adaptive routing approaches over the same subnet-based diagonal mesh (SDmesh) network and reported.
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Year | DOI | Venue |
|---|---|---|
2020 | 10.1145/3387928 | ACM Transactions on Embedded Computing Systems |
Keywords | DocType | Volume |
Network-on-chip,NoC routing,congestion-aware NoC design,performance | Journal | 19 |
Issue | ISSN | Citations |
4 | 1539-9087 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tuhin Subhra Das | 1 | 5 | 2.87 |
| Prasun Ghosal | 2 | 51 | 22.38 |
| Navonil Chatterjee | 3 | 26 | 6.21 |
| Arnab Nath | 4 | 0 | 0.34 |
| Akash Banerjee | 5 | 0 | 0.34 |
| Subhojyoti Khastagir | 6 | 0 | 0.34 |