Author Info
Name
Affiliation
Papers
NAVONIL CHATTERJEE
School of VLSI Technology, Bengal Engineering and Science University, India
17
Collaborators
Citations 
PageRank 
17
26
6.21
Referers 
Referees 
References 
56
392
226
Search Limit
100392
Title
Citations
PageRank
Year
Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors00.342021
A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing.00.342021
Dynamic task allocation and scheduling with contention-awareness for Network-on-Chip based multicore systems00.342021
Thermal-aware detour routing in 3D NoCs.00.342020
Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing00.342020
A Permanent Fault Tolerant Dynamic Task Allocation Approach for Network-on-Chip based Multicore Systems00.342019
Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems.00.342019
Virtual circuit switch based orderly delivery of packets in adaptive NoC routing00.342019
A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent Faults10.342018
Reliability-aware application mapping onto mesh based Network-on-Chip.10.342018
Task mapping and scheduling for network-on-chip based multi-core platform with transient faults.20.352018
Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform80.512017
Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform.60.452017
A strategy for fault tolerant reconfigurable Network-on-Chip design00.342016
Fault Tolerant Mesh Based Network-On-Chip Architecture10.362015
A spare router based reliable Network-on-Chip design70.472014
VLSI architecture for spatial domain spread spectrum image watermarking using gray-scale watermark00.342012