Name
Title | ||
|---|---|---|
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability |
Abstract | ||
|---|---|---|
Random number generation is integral to information security in IoT based cyber-physical systems. One such recent scheme of random number generation was proposed in [1] called Mageto, which is based on the design principles of cellular automata (CA). CA are characterized as finite state machines (FSMs) which evolve in discrete time steps. In hardware, their architecture remains modular and cascadable, which is ideal for amicable mapping onto FPGA primitives, leading to a speed-area efficient realization [2], [3]. Fault localization and in-system testing of FPGAs are now assuming substantial importance [4]. Exploring the utilization ratio of the configured primitives is often essential for supplementing an original FPGA implementation with testable logic without appreciable hardware overhead and critical path delay, by adopting careful optimization practices. Primitive instantiation is one such technique to directly instantiate an FPGA primitive into a design through appropriate logic configuration. We believe that VLSI implementation of Mageto has never been discussed before, which we choose to address in this paper. Our proposed primitive instantiation based architectures for Mageto, whose design description generation has been automated, outperform the relatively high level behavioral implementations with respect to area (logic slices) and speed. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/FCCM48280.2020.00038 | 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) |
Keywords | DocType | ISSN |
primitive instantiation,FPGA primitive,appropriate logic configuration,design description generation,speed-area efficient architecture design,cellular automata,Mageto logic,built-in testability,random number generation,information security,cyber-physical systems,finite state machines,speed-area efficient realization,configured primitives,FPGA implementation,appreciable hardware overhead,VLSI implementation | Conference | 2576-2613 |
ISBN | Citations | PageRank |
978-1-7281-5804-4 | 0 | 0.34 |
References | Authors | |
3 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayan Palchaudhuri | 1 | 11 | 7.67 |
| Anindya Sundar Dhar | 2 | 97 | 26.09 |