Paper Info
Title
Dissecting the CUDA scheduling hierarchy: a Performance and Predictability Perspective
Abstract
Over the last few years, the ever-increasing use of Graphic Processing Units (GPUs) in safety-related domains has opened up many research problems in the real-time community. The closed and proprietary nature of the scheduling mechanisms deployed in NVIDIA GPUs, for instance, represents a major obstacle in deriving a proper schedulability analysis for latency-sensitive applications. Existing literature addresses these issues by either (i) providing simplified models for heterogeneous CPUGPU systems and their associated scheduling policies, or (ii) providing insights about these arbitration mechanisms obtained through reverse engineering. In this paper, we take one step further by correcting and consolidating previously published assumptions about the hierarchical scheduling policies of NVIDIA GPUs and their proprietary CUDA application programming interface. We also discuss how such mechanisms evolved with recently released GPU micro-architectures, and how such changes influence the scheduling models to be exploited by real-time system engineers.
Year
DOI
Venue
2020
10.1109/RTAS48715.2020.000-5
2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)
Keywords
DocType
ISSN
hierarchical scheduling policies,NVIDIA GPUs,CUDA application programming interface,GPU microarchitectures,scheduling models,real-time system engineers,CUDA scheduling hierarchy,Graphic Processing Units,safety-related domains,latency-sensitive applications,heterogeneous CPUGPU systems,associated scheduling policies,arbitration mechanisms,reverse engineering,schedulability analysis
Conference
1545-3421
ISBN
Citations 
PageRank 
978-1-7281-5500-5
1
0.35
References 
Authors
9
5
Name
Order
Citations
PageRank
Ignacio Sanudo Olmedo172.88
Nicola Capodieci28216.13
Jorge Martínez39517.02
Andrea Marongiu433739.19
Marko Bertogna5101056.16