Name
Abstract | ||
|---|---|---|
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging non-volatile memory technology, as a leading candidate to replace conventional on-chip memories due to its various advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility. However, read and write operations in STT-MRAM are extremely vulnerable to manufacturing variations. In particular, the read operation is becoming more susceptible to failures since the read timing and read-disturb failures have conflicting requirements of read period. To overcome this issue, we propose a technique to reduce the read period without sacrificing the target reliability requirements. The reduced read period, in turn, results in improved read performance and reduced read-disturb rates. The results show that using this technique, the read period can be reduced by 50%, and the read-disturb probability by 51%. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/VTS48691.2020.9107605 | 2020 IEEE 38th VLSI Test Symposium (VTS) |
Keywords | DocType | ISSN |
STT-MRAM,spin transfer torque magnetic random access memory,nonvolatile memory technology,on-chip memories,improved read performance,read failure mitigation,CMOS compatibility,read and write operations,read-disturb failures,target reliability requirements,read-disturb probability | Conference | 1093-0167 |
ISBN | Citations | PageRank |
978-1-7281-5360-5 | 0 | 0.34 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sarath Mohanachandran Nair | 1 | 17 | 5.91 |
| Rajendra Bishnoi | 2 | 132 | 19.64 |
| Mehdi B. Tahoori | 3 | 1537 | 163.44 |