Name
Abstract | ||
|---|---|---|
28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier Degradation (HCD) under varying gate/drain (V
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/V
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) bias and temperature (T: 300K to 77K). A compact model is used to partition measured threshold voltage shift (ΔV
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) into interface trap generation due to pure HCD (ΔV
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), Bias Temperature Instability (BTI, ΔV
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), and electron/hole trapping (ΔV
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/ΔV
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) subcomponents. The relative importance of the subcomponents is analyzed for varying T. Although pure HCD dominates under Cryo-CMOS operation, the T dependence is shown to be different for Si NMOS and SiGe PMOS FETs. Finally, the impact on the circuit (RO: Ring Oscillator) operation is analyzed. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/IRPS45951.2020.9129312 | 2020 IEEE International Reliability Physics Symposium (IRPS) |
Keywords | DocType | ISSN |
BTI,HCD,Cryo-CMOS,HKMG,trap generation,charge trapping,RO | Conference | 1541-7026 |
ISBN | Citations | PageRank |
978-1-7281-3199-3 | 1 | 0.39 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| W. Chakraborty | 1 | 1 | 0.39 |
| U. Sharma | 2 | 1 | 0.39 |
| Suman Datta | 3 | 415 | 51.93 |
| Mahapatra, S. | 4 | 22 | 4.83 |