Title
EDSSA: An Encoder-Decoder Semantic Segmentation Networks Accelerator on OpenCL-Based FPGA Platform.
Abstract
Visual semantic segmentation, which is represented by the semantic segmentation network, has been widely used in many fields, such as intelligent robots, security, and autonomous driving. However, these Convolutional Neural Network (CNN)-based networks have high requirements for computing resources and programmability for hardware platforms. For embedded platforms and terminal devices in particular, Graphics Processing Unit (GPU)-based computing platforms cannot meet these requirements in terms of size and power consumption. In contrast, the Field Programmable Gate Array (FPGA)-based hardware system not only has flexible programmability and high embeddability, but can also meet lower power consumption requirements, which make it an appropriate solution for semantic segmentation on terminal devices. In this paper, we demonstrate EDSSA-an Encoder-Decoder semantic segmentation networks accelerator architecture which can be implemented with flexible parameter configurations and hardware resources on the FPGA platforms that support Open Computing Language (OpenCL) development. We introduce the related technologies, architecture design, algorithm optimization, and hardware implementation of the Encoder-Decoder semantic segmentation network SegNet as an example, and undertake a performance evaluation. Using an Intel Arria-10 GX1150 platform for evaluation, our work achieves a throughput higher than 432.8 GOP/s with power consumption of about 20 W, which is a 1.2x times improvement the energy-efficiency ratio compared to a high-performance GPU.
Year
DOI
Venue
2020
10.3390/s20143969
SENSORS
Keywords
DocType
Volume
FPGA,semantic segmentation,framework,OpenCL
Journal
20
Issue
ISSN
Citations 
14.0
1424-8220
0
PageRank 
References 
Authors
0.34
0
8
Name
Order
Citations
PageRank
Hongzhi Huang100.34
Yakun Wu200.34
Mengqi Yu300.34
Xuesong Shi400.34
Fei Qiao59435.38
Li Luo652.89
Qi Wei74920.68
Xin-Jun Liu83510.04