Name
Abstract | ||
|---|---|---|
High-Level-Synthesis can be used to generate hardware accelerators for compute intense software parts (so called kernels). For meaningful acceleration, such kernels should be able to autonomously access the memory. Unfortunately, such memory accesses can constitute dependences (e.g. writing an array before reading from it) leading to bottlenecks. The analysis of potential conflicts of memory accesses is often difficult and in many cases not even possible. In order to improve the scheduling of memory accesses, we propose a novel methodology to fully automatically place bypasses and squashes into the data flow graph that is used to generate the hardware accelerator. Evaluating our approach with the Powerstone benchmark suite, we can show that execution time is reduced on average by 6.5%. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/IPDPSW50202.2020.00020 | 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Keywords | DocType | ISSN |
High-Level-Synthesis,Memory Dependences,FPGA,Memory Disambiguation,Write Squashing,Bypassing | Conference | 2164-7062 |
ISBN | Citations | PageRank |
978-1-7281-7457-0 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Johanna Rohde | 1 | 0 | 0.34 |
| Karsten Müller | 2 | 0 | 0.34 |
| Christian Hochberger | 3 | 457 | 99.51 |