Name
Abstract | ||
|---|---|---|
This paper presents an efficient hardware architecture able to perform 2D dilated convolutions and suitable for the integration within modern heterogeneous embedded systems targeting semantic image segmentation. The proposed design supports multiple dilation rates. Moreover, it uses limited amounts of resources even when large convolution windows are processed. As a case study, the novel circuit has been integrated within a Xilinx Zynq-7000 FPSoC device to accelerate a state-of-the-art CNN model for medical images segmentation. Obtained results demonstrate that higher computational capabilities, reduced resources utilization and lower power consumption are achieved with respect to the competitors existing in literature. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ASAP49362.2020.00022 | 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP) |
Keywords | DocType | ISSN |
dilated convolution,à-trous spatial pyramid pooling,segmentation FCNs,FPGA,heterogeneous embedded systems | Conference | 2160-0511 |
ISBN | Citations | PageRank |
978-1-7281-7279-8 | 0 | 0.34 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cristian Sestito | 1 | 0 | 0.34 |
| Fanny Spagnolo | 2 | 8 | 4.00 |
| Pasquale Corsonello | 3 | 278 | 38.06 |
| Stefania Perri | 4 | 264 | 33.11 |