Name
Abstract | ||
|---|---|---|
SAT Attack, CycSAT, and Removal Attack have demonstrated their abilities to break most existing logic locking methods. In this article, we propose a new cyclic logic locking method to invalidate these attacks simultaneously. Our main intention is to create noncombinational cycles to lock a circuit. Specifically, the noncombinational behavior in the noncombinational cycles that is unobservable at the primary outputs (POs) needs to be preserved when the correct key-vector is fed to resist CycSAT, and the noncombinational behavior in the noncombinational cycles affecting POs needs to be preserved when the incorrect key-vector is fed to invalidate SAT Attack. Furthermore, some nodes will be removed when applying our locking method, which is able to defend Removal Attack. The experimental results show the effectiveness and low area overhead of the proposed method. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCAD.2019.2960351 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Optimization,Logic gates,Security,Electronics packaging,Delays,Integrated circuits,Inverters | Journal | 39 |
Issue | ISSN | Citations |
10 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsiao-Yu Chiang | 1 | 0 | 0.68 |
| Yung-Chih Chen | 2 | 413 | 39.89 |
| De-Xuan Ji | 3 | 0 | 0.34 |
| Xiang-Min Yang | 4 | 0 | 0.68 |
| Chia-Chun Lin | 5 | 128 | 15.00 |
| Wang Chun-Yao | 6 | 251 | 36.08 |