Name
Abstract | ||
|---|---|---|
This brief presents a memory based fast binary logarithmic converter based on a piecewise linear approximation technique. The proposed method is simple and arithmetic operation-less, which achieves 10
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−4</sup>
to 10
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup>
maximum absolute error (MAE) while maintaining a high speed. The approach partitions the logarithmic curve of the fractional component into
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{L}$ </tex-math></inline-formula>
uniform regions and a block RAM (size
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{L} \times $ </tex-math></inline-formula>
bits) stores the approximate value of each sub-region. For any number, most significant
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$ </tex-math></inline-formula>
bits of the fractional component address the memory location of the logarithmic converter. The hardware synthesis result, implemented with 26 bits fractional precision on Virtex-6 field-programmable gate array device, shows 75% improvement in MAE and 27% decrease in critical path delay compared to the current state-of-the-art techniques in the worst-case scenario. In Otsu’s image thresholding algorithm, the proposed logarithmic converter with 3.08 (
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=2^{8} \times 12$ </tex-math></inline-formula>
) kbits memory size adequately meets the accuracy requirement for improved image segmentation. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCSII.2019.2945336 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | DocType | Volume |
Hardware,Image segmentation,Interpolation,Circuits and systems,Delays,Memory management,Design methodology | Journal | 67 |
Issue | ISSN | Citations |
10 | 1549-7747 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Biswabandhu Jana | 1 | 0 | 1.35 |
| Avishek Sinha Roy | 2 | 0 | 1.35 |
| Goutam Saha | 3 | 255 | 23.17 |
| Swapna Banerjee | 4 | 196 | 30.07 |